The present disclosure herein relates to a semiconductor memory device, and more particularly, to a discharge circuit which discharges terminals of a memory array of a nonvolatile semiconductor memory device.
In nonvolatile semiconductor memory devices, an example of which is a flash memory, device operations generally include a write operation for writing information in memory cells, a read operation for reading written information from the memory cells, and an erase operation for erasing memory cells to allow execution of a new write operation (i.e., rewrite operation).
The erase operation includes a discharge process which is executed after memory cells are erased.
FIG. 7 is a schematic block diagram illustrating a nonvolatile semiconductor memory device disclosed in Japanese Patent Publication No. 10-2002-0261172 (the JP '172 reference).
Referring to FIG. 7, each of a plurality of floating gate type MOS transistors Tr arranged in an array includes a source 13, a drain 14, a floating gate 16, and a control gate 18. Herein, the source 13 and the drain 14 are formed in a P-well 12 that is disposed in the N-well of the P-type semiconductor substrate 10, and the floating gate 16 is formed by fabricating a tunnel oxide layer 15 as a dielectric on the source 13 and the drain 14. The control gate 18 is formed by fabricating an interlayer dielectric 17 as a dielectric on the floating gate 16.
In a voltage condition during execution of an erase operation of the floating gate type MOS transistor Tr, the drain 14 has an opened state, and a first voltage (for example, 6 V) is applied to the P-well 12. At this point, a voltage of 9V is applied to the control gate 18 and simultaneously a second voltage (for example, 9 V) is applied to the N-well 11. Based on this voltage condition, electrons are detached from the floating gate 16, and thus the threshold voltage of the floating gate type MOS transistor Tr becomes low. An erase circuit for realizing the voltage conditions of the erase operation includes a negative voltage pump circuit 3 for applying a negative voltage to a word line WD through a row decoder circuit RD. In addition, the erase circuit includes a first high voltage pump circuit 1 for applying a voltage of 6 V to the P-well 12, and a second high voltage pump circuit 2 for applying a voltage of 9 V to the N-well 11.
When the application of a pulse is ended, an operation is performed which recovers the voltage of the P-well 12 and the voltage of the word line WD to a reference voltage (Vss) (for example, 0 V). The signal of a P-well switch 4 has a low level, the word line WD is forced into the reference voltage (Vss), and the P-well 12 is forced into the reference voltage (Vss). FIG. 8 is a diagram illustrating an example of a voltage waveform of the word line WD, a voltage waveform of the N-well 11 and a voltage waveform of the P-well 12. In a section where the voltage of the word line WD is forced from a voltage of −9 V into the reference voltage (Vss), the voltage of the P-well 12 is boosted from 6 V by about 2 V to become about 8 V and is forced into the reference voltage (Vss). At this point, since the N-well 11 is coupled to the P-well 12, the voltage of the P-well 12 is shifted from 6 V to 8 V, but the voltage of the N-well 11 is shifted from 9 V to 10 V.
In this way, since the voltage of the N-well 11 is always higher than that of the P-well 12, a forward current from the P-well 12 to the N-well 11 does not flow. As a result, the occurrence of latchup condition can be avoided. In a discharge process after erasure in FIG. 8, however, while the voltage of the word line WD is forced into the reference voltage (Vss), since the voltage of the P-well 12 is boosted through coupling and is forced into the reference voltage (Vss), the time necessary for discharge becomes longer to about 500 ns.
Japanese Patent Publication No. 10-2005-0310301 (the JP '301 reference) discloses a nonvolatile semiconductor memory device that includes a nonvolatile memory cell, a word line, a first charge pump circuit, and a discharge circuit. The nonvolatile memory cell includes a first MOS transistor. The word line is connected to the nonvolatile memory cell and the control gate of the first MOS transistor that is disposed on the same line with the nonvolatile memory cell. The first charge pump circuit is activated when data is written or erased to/from the memory cell and generates a first voltage to supply the first voltage to the word line. A discharge circuit discharges an electric charge, which is generated by the first charge pump circuit, to a ground potential terminal or a power source potential terminal while flowing a current in a first voltage node when the first charge pump circuit is deactivated.
For a reset operation after the end of an erase operation, in a state where the potential of a node VDDW is maintained to a voltage VPP, the potential of a node VNEG is again shifted to 0 V and thereby the node VNEG is set to 0 V, and the potential of the node VDDW is set to a voltage Vcc2 and then is set to 0 V, thereby decreasing the effect of a coupling noise. Herein, the node VNEG is set to 0 V, and thereafter, the potential of the node VDDW is set to the voltage Vcc2 and then is set to 0 V. Consequently, it is estimated that technique of the JP '301 reference requires a discharge time longer than the discharge time of 500 ns necessary for a discharge process as in the JP '172 reference.
Japanese Patent Publication No. 10-2001-0351390 discloses an erase circuit control device of a flash memory including a common discharge circuit that electrically and directly connects a gate to at least one of a substrate, a source and a drain which configure cells MC00 to MCmm forming the cell array of a flash memory circuit, during an erase operation.
In an operation executed when erasure has ended, a discharge control signal is shifted from an L level to an H level and thus all N-type MOSFETs of a discharge control circuit are turned on. Therefore, the source CSL, substrate CWL, drain CBL and node Vneg that are electrically connected to the respective contact points of the source, substrate, drain and gate of a memory cell is connected to a common discharge contact point and thereby an N-type MOSFET is turned on, and thus a current path between the common discharge contact point and a ground potential is secured. In this way, since a terminal having a positive potential and a terminal having a negative potential are shorted through a switch, it is difficult to control a discharge time, and thus the withstanding voltage of a device configuring the switch is required to become high. Moreover, a switch size is required to be enlarged in accordance with an element for discharge.
In Japanese Patent Publication No. 10-2008-0004236, disclosed is an erase discharge method of a nonvolatile semiconductor memory device that includes a first step, a second step and a third step. The first step performs an erase operation that applies a first voltage to a word line, applies a second voltage to an N-well and a P-well, opens a bit line and a ground line, and detaches electric charges, which are accumulated in the floating gate of a floating gate type Field Effect Transistor (FET), from a semiconductor substrate. The second step shifts the potential of the word line and the potential of the bit line to a ground potential, discharges electric charges that are accumulated in the word line, and turns on a discharge transistor that is connected to the bit line. The third step shifts the potential of the N-well and the potential of the P-well to a ground potential, and discharges electric charges that are accumulated in the N-well and the P-well.
The second step connects a discharge transistor 1 to a bit line and discharges the bit line simultaneously with the discharge of the word line, and thus prevents the overshooting of the bit line through capacitive coupling between the word line and the bit line. In this way, for preparing a discharge circuit for preventing the voltage of the bit line from rising through coupling in bit line units or in each local bit line of a memory array, the complexity of a circuit increases and simultaneously the manufacturing cost inevitably rises.